At the same time, the emitter of Q2 is at ground potential, keeping Q4 OFF. Since Q3 acts as a emitter follower, by providing a low impedance path from Vcc to the output, making the output into HIGH. The collector of Q2 is HIGH and turns Q3 into saturation. Hence there is no current into the base of Q2 and making it into cur-off. Then there is a current from Vcc through R1 ti the base emitter junction of Q1 and into the LOW input, which provides a path to the ground for the current. If A or B is low, the base-emitter junction of Q1 is forward biased and its base-collector junction is reverse biased. the output transistors Q3 and Q4 form a totem-pole output arrangement. For the most part, we will consider the input transistor, act just like two diodes.Ī two input standard TTL NAND gate is a multiple emitter transistor for the inputs A and B. The analysis of this circuit follows very much the same path as the analysis of the DTL gate. Later on, we will make additional modifications to this circuit to improve its performance further. The input diodes are replaced by the multi-emitter NPN transistor. The p-n junction of diode is replaced by the BE junction of transistor and with the current gain of the transistor, the current going into the base of transistor is greatly increased, increasing the fanout. For example, the diode in the DTL can be replaced by a transistor whose collector is pulled up to the power supply. The evolution from Diode transistor Logic to transistor transistor Logic can be seen by observing the placement of p-n junctions.

Totem pole output what is